INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987 Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. Intel retains the right to make changes to these specifications at any time, without notice. Contact your local sales office to obtain the latest specifications before placing your order. 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Additional copies of this manual or other Intel literature may be obtained from: Intel Corporation Literature Distribution Mail Stop SC6-59 3065 Bowers Avenue Santa Clara, CA 95051 (c)INTEL CORPORATION 1987 CG-10/86 Preface DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD An Introduction to the 80287 This supplement describes the 80287 Numeric Processor Extension (NPX) for the 80286 microprocessor. Below is a brief overview of 80286 concepts, along with some of the nomenclature used throughout this and other Intel publications. The 80286 Microsystem The 80286 is a new VLSI microprocessor system with exceptional capabilities for supporting large-system applications. Based on a new-generation CPU (the Intel 80286), this powerful microsystem is designed to support multiuser reprogrammable and real-time multitasking applications. Its dedicated system support circuits simplify system hardware; sophisticated hardware and software tools reduce both the time and the cost of product development. The 80286 is a virtual-memory microprocessor with on-chip memory management and protection. The 80286 microsystem offers a total-solution approach, enabling you to develop high-speed, interactive, multiuser, multitaskingDD and multiprocessorDDsystems more rapidly and at higher performance than ever before. ~ Reliability and system up-time are becoming increasingly important in all applications. Information must be protected from misuse or accidental loss. The 80286 includes a sophisticated and flexible four-level protection mechanism that isolates layers of operating system programs from application programs to maintain a high degree of system integrity. ~ The 80286 provides 16 megabytes of physical address space to support today's application requirements. This large physical memory enables the 80286 to keep many large programs and data structures simultaneously in memory for high-speed access. ~ For applications with dynamically changing memory requirements, such as multiuser business systems, the 80286 CPU provides on-chip memory management and virtual memory support. On an 80286-based system, each user can have up to a gigabyte (2^(30) bytes) of virtual-address space. This large address space virtually eliminates restrictions on the number or size of programs that may be part of the system. ~ Large multiuser or real-time multitasking systems are easily supported by the 80286. High-performance features, such as a very high-speed task switch, fast interrupt-response time, inter-task protection, and a quick and direct operating system interface, make the 80286 highly suited to multiuser/multitasking applications. ~ The 80286 has two operating modes: Real-Address mode and Protected-Address mode. In Real-Address mode, the 80286 is fully compatible with the 8086, 8088, 80186, and 80188 microprocessors; all of the extensive libraries of 8086 and 8088 software execute four to six times faster on the 80286, without any modification. ~ In Protected-Address mode, the advanced memory management and protection features of the 80286 become available, without any reduction in performance. Upgrading 8086 and 8088 application programs to use these new memory management and protection features usually requires only reassembly or recompilation (some programs may require minor modification). This compatibility between 80286 and 8086 processor families reduces both the time and the cost of software development. The Organization of This Manual This manual describes the 80287 Numeric Processor Extension (NPX) for the 80286 microprocessor. The material in this manual is presented from the perspective of software designers, both at an applications and at a systems software level. ~ Chapter One, "Overview of Numeric Processing," gives an overview of the 80287 NPX and reviews the concepts of numeric computation using the 80287. ~ Chapter Two, "Programming Numeric Applications," provides detailed information for software designers generating applications for systems containing an 80286 CPU with an 80287 NPX. The 80286/80287 instruction set mnemonics are explained in detail, along with a description of programming facilities for these systems. A comparative 80287 programming example is given. ~ Chapter Three, "System-Level Numeric Programming," provides information of interest to systems software writers, including details of the 80287 architecture and operational characteristics. ~ Chapter Four, "Numeric Programming Examples," provides several detailed programming examples for the 80287, including conditional branching, the conversion between floating-point values and their ASCII representations, and the calculation of several trigonometric functions. These examples illustrate assembly-language programming on the 80287 NPX. ~ Appendix A, "Machine Instruction Encoding and Decoding," gives reference information on the encoding of NPX instructions. ~ Appendix B, "Compatability between the 80287 NPX and the 8087," describes the differences between the 80287 and the 8087. ~ Appendix C, "Implementing the IEEE P754 Standard," gives details of the IEEE P754 Standard. ~ The Glossary defines 80287 and floating-point terminology. Refer to it as needed. Related Publications To best use the material in this manual, readers should be familiar with the operation and architecture of 80286 systems. The following manuals contain information related to the content of this supplement and of interest to programmers of 80287 systems: ~ Introduction to the 80286, order number 210308 ~ ASM286 Assembly Language Reference Manual, order number 121924 ~ 80286 Operating System Writer's Guide, order number 121960 ~ 80286 Hardware Reference Manual, order number 210760 ~ Microprocessor and Peripheral Handbook, order number 210844 ~ PL/M-286 User's Guide, order number 121945 ~ 80287 Support Library Reference Manual, order number 122129 ~ 8086 Software Toolbox Manual, order number 122203 (includes information about 80287 Emulator Software) Notational Conventions This manual uses special notation to represent sub- and superscript characters. Subscript characters are surrounded by {curly brackets}, for example 10{2} = 10 base 2. Superscript characters are preceeded by a caret and enclosed within (parentheses), for example 10^(3) = 10 to the third power. Table of Contents DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD Preface Chapter 1 Overview of Numeric Processing Introduction to the 80287 Numeric Processor Extension Performance Ease of Use Applications Upgradability Programming Interface Hardware Interface 80287 Numeric Processor Architecture The NPX Register Stack The NPX Status Word Control Word The NPX Tag Word The NPX Instruction and Data Pointers Computation Fundamentals Number System Data Types and Formats Binary Integers Decimal Integers Real Numbers Rounding Control Precision Control Infinity Control Special Computational Situations Special Numeric Values Nonnormal Real Numbers Denormals and Gradual Underflow UnnormalsDDDescendents of Denormal Operands Zeros and Pseudo Zeros Infinity NaN (Not a Number) Indefinite Encoding of Data Types Numeric Exceptions Invalid Operation Zero Divisor Denormalized Operand Numeric Overflow and Underflow Inexact Result Handling Numeric Errors Automatic Exception Handling Software Exception Handling Chapter 2 Programming Numeric Applications The 80287 NPX Instruction Set Compatibility with the 8087 NPX Numeric Operands Data Transfer Instructions Arithmetic Instructions Comparison Instructions Transcendental Instructions Constant Instructions Processor Control Instructions Instruction Set Reference Information Instruction Execution Time Bus Transfers Instruction Length Programming Facilities High-Level Languages PL/M-286 ASM286 Defining Data Records and Structures Addressing Modes Comparative Programming Example 80287 Emulation Concurrent Processing with the 80287 Managing Concurrency Instruction Synchronization Data Synchronization Error Synchronization Incorrect Error Synchronization Proper Error Synchronization Chapter 3 System-Level Numeric Programming 80287 Architecture Processor Extension Data Channel Real-Address Mode and Protected Virtual-Address Mode Dedicated and Reserved I/O Locations Processor Initialization and Control System Initialization Recognizing the 80287 NPX Configuring the Numerics Environment Initializing the 80287 80287 Emulation Handling Numeric Processing Exceptions Simultaneous Exception Response Exception Recovery Examples Chapter 4 Numeric Programming Examples Conditional Branching Examples Exception Handling Examples Floating-Point to ASCII Conversion Examples Function Partitioning Exception Considerations Special Instructions Description of Operation Scaling the Value Inaccuracy in Scaling Avoiding Underflow and Overflow Final Adjustments Output Format Trigonometric Calculation Examples FPTAN and FPREM Cosine Uses Sine Code Appendix A Machine Instriction Encoding and Decoding Appendix B Compatibility Between the 80287 NPX and the 8087 Appendix C Implementing The IEEE P754 Standard Options implemented in the 80287 Areas of the Standard Implemented in Software Additional Software to Meet the Standard Glossary of 80287 and Floating-Point Terminology Index Figures 1-1 Evolution and Performance of Numeric Processors 1-2 80287 NPX Block Diagram 1-3 80287 Register Set 1-4 80287 Status Word 1-5 80287 Control Word Format 1-6 80287 Tag Word Format 1-7 80287 Instruction and Data Pointer Image in Memory 1-8 80287 Number System 1-9 Data Formats 1-10 Projective versus Affine Closure 1-11 Arithmetic Example Using Infinity 2-1 FSAVE/FRSTOR Memory Layout 2-2 FSTENV/FLDENV Memory Layout 2-3 Sample 80287 Constants 2-4 Status Word RECORD Definition 2-5 Structure Definition 2-6 Sample PL/M-286 Program 2-7 Sample ASM286 Program 2-8 Instructions and Register Stack 2-9 Synchronizing References to Shared Data 2-10 Documenting Data Synchronization 2-11 Nonconcurrent FIST Instruction Code Macro 2-12 Error Synchronization Examples 3-1 Software Routine to Recognize the 80287 4-1 Conditional Branching for Compares 4-2 Conditional Branching for FXAM 4-3 Full-State Exception Handler 4-4 Reduced-Latency Exception Handler 4-5 Reentrant Exception Handler 4-6 Floating-Point to ASCII Conversion Routine 4-7 Calculating Trigonometric Functions Tables 1-1 Numeric Processing Speed Comparisons 1-2 Numeric Data Types 1-3 Principal NPX Instructions 1-4 Interpreting the NPX Condition Codes 1-5 Real Number Notation 1-6 Rounding Modes 1-7 Denormalization Process 1-8 Exceptions Due to Denormal Operands 1-9 Unnormal Operands and Results 1-10 Zero Operands and Results 1-11 Masked Overflow Response with Directed Rounding 1-12 Infinity Operands and Results 1-13 Binary Integer Encodings 1-14 Packed Decimal Encodings 1-15 Real and Long Real Encodings 1-16 Temporary Real Encodings 1-17 Exception Conditions and Masked Responses 2-1 Data Transfer Instructions 2-2 Arithmetic Instructions 2-3 Basic Arithmetic Instructions and Operands 2-4 Condition Code Interpretation after FPREM 2-5 Comparison Instructions 2-6 Condition Code Interpretation after FCOM 2-7 Condition Code Interpretation after FTST 2-8 FXAM Condition Code Settings 2-9 Transcendental Instructions 2-10 Constant Instructions 2-11 Processor Control Instructions 2-12 Key to Operand Types 2-13 Execution Penalties 2-14 Instruction Set Reference Data 2-15 PL/M-286 Built-In Procedures 2-16 80287 Storage Allocation Directives 2-17 Addressing Mode Examples 3-1 NPX Processor State Following Initialization 3-2 Precedence of NPX Exceptions A-1 80287 Instruction Encoding A-2 Machine Instruction Decoding Guide Chapter 1 Overview of Numeric Processing DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD The 80287 NPX is a high-performance numerics processing element that extends the 80286 architecture by adding significant numeric capabilities and direct support for floating-point, extended-integer, and BCD data types. The 80286 CPU with 80287 NPX easily supports powerful and accurate numeric applications through its implementation of the proposed IEEE 754 Standard for Binary Floating-Point Arithmetic. Introduction to the 80287 Numeric Processor Extension The 80287 Numeric Processor Extension (NPX) is highly compatible with its predecessor, the earlier Intel 8087 NPX. The 8087 NPX was designed for use in 8086-family systems. The 8086 was the first microprocessor family to partition the processing unit to permit high-performance numeric capabilities. The 8087 NPX for this processor family implemented a complete numeric processing environment in compliance with the proposed IEEE 754 Floating-Point Standard. With the 80287 Numeric Processor Extension, high-speed numeric computations have been extended to 80286 high-performance multi-tasking and multi-user systems. Multiple tasks using the numeric processor extension are afforded the full protection of the 80286 memory management and protection features. Figure 1-1 illustrates the relative performance of 8-MHz 8086/8087 and 80286/80287 systems in executing numerics-oriented applications. Figure 1-1. Evolution and Performance of Numeric Processors DOUBLE-PRECISION  ZDDDDDDDDDDDDD? WHETSTONE 3 3 80286/80287 3 PERFORMANCE 3 @DDDDDDDDDDDDY (KOPS) 200 DED  3  3 ZDDDDDDDDDD? 3 3 8086/8087 3 3 @DDDDDDDDDDDY 3 100 DED 3 3 3 3 @DDDDDDDDDDDDEDDDDDDDDDDDDEDDDDDDDDDDD 1980 1983 YEAR INTRODUCED Performance Table 1-1 compares the execution times of several 80287 instructions with the equivalent operations executed in software on an 8-MHz 80286. The software equivalents are highly-optimized assembly-language procedures from the 80287 emulator. As indicated in the table, the 80287 NPX provides about 50 to 100 times the performance of software numeric routines on the 80286 CPU. An 8-MHz 80287 multiplies 32-bit and 64-bit real numbers in about 11.9 and 16.9 microseconds, respectively. Of course, the actual performance of the NPX in a given system depends on the characteristics of the individual application. Although the performance figures shown in table 1-1 refer to operations on real (floating-point) numbers, the 80287 also manipulates fixed-point binary and decimal integers of up to 64 bits or 18 digits, respectively. The 80287 can improve the speed of multiple-precision software algorithms for integer operations by 10 to 100 times. Because the 80287 NPX is an extension of the 80286 CPU, no software overhead is incurred in setting up the NPX for computation. The 80287 and 80286 processors coordinate their activities in a manner transparent to software. Moreover, built-in coordination facilities allow the 80286 CPU to proceed with other instructions while the 80287 NPX is simultaneously executing numeric instructions. Programs can exploit this concurrency of execution to further increase system performance and throughput. Table 1-1. Numeric Processing Speed Comparisons Approximate Performance Ratios: 8 MHz 80287 to 8 MHz Protected Mode iAPX ZDDDDDD Floating-Point Instruction DDDDDDDDDDDD? using E80287 FADD ST,ST (Temp Real) Addition 1: 42 FDIV DWORD PTR (Single-Precision) Division 1:266 FXAM (Stack(0) assumed) Examine 1:139 FYL2X (Stack(0),(1) assumed) Logarithm 1: 99 FPATAN (Stack(0) assumed) Arctangent 1:153 F2XM1 (Stack (0) assumed) Exponentiation 1: 41 Ease of Use The 80287 NPX offers more than raw execution speed for computation-intensive tasks. The 80287 brings the functionality and power of accurate numeric computation into the hands of the general user. Like the 8087 NPX that preceded it, the 80287 is explicitly designed to deliver stable, accurate results when programmed using straightforward "pencil and paper" algorithms. The IEEE 754 standard specifically addresses this issue, recognizing the fundamental importance of making numeric computations both easy and safe to use. For example, most computers can overflow when two single-precision floating-point numbers are multiplied together and then divided by a third, even if the final result is a perfectly valid 32-bit number. The 80287 delivers the correctly rounded result. Other typical examples of undesirable machine behavior in straightforward calculations occur when solving for the roots of a quadratic equation: -b q {(b} - 4ac) DDDDDDDDDDDDDDDDDDDD 2a for computing financial rate of return, which involves the expression: (1+i)^(n). On most machines, straightforward algorithms will not deliver consistently correct results (and will not indicate when they are incorrect). To obtain correct results on traditional machines under all conditions usually requires sophisticated numerical techniques that are foreign to most programmers. General application programmers using straightforward algorithms will produce much more reliable programs using the 80287. This simple fact greatly reduces the software investment required to develop safe, accurate computation-based products. Beyond traditional numerics support for scientific applications, the 80287 has built-in facilities for commercial computing. It can process decimal numbers of up to 18 digits without round-off errors, performing exact arithmetic on integers as large as 2^(64) or 10^(18). Exact arithmetic is vital in accounting applications where rounding errors may introduce monetary losses that cannot be reconciled. The NPX contains a number of optional facilities that can be invoked by sophisticated users. These advanced features include two models of infinity, directed rounding, gradual underflow, and either automatic or programmed exception-handling facilities. These automatic exception-handling facilities permit a high degree of flexibility in numeric processing software, without burdening the programmer. While performing numeric calculations, the NPX automatically detects exception conditions that can potentially damage a calculation. By default, on-chip exception handlers may be invoked to field these exceptions so that a reasonable result is produced, and execution may proceed without program interruption. Alternatively, the NPX can signal the CPU, invoking a software exception handler whenever various types of exceptions are detected. Applications The NPX's versatility and performance make it appropriate to a broad array of numeric applications. In general, applications that exhibit any of the following characteristics can benefit by implementing numeric processing on the 80287: ~ Numeric data vary over a wide range of values, or include nonintegral values. ~ Algorithms produce very large or very small intermediate results. ~ Computations must be very precise; i.e., a large number of significant digits must be maintained. ~ Performance requirements exceed the capacity of traditional microprocessors. ~ Consistently safe, reliable results must be delivered using a programming staff that is not expert in numerical techniques. Note also that the 80287 can reduce software development costs and improve the performance of systems that use not only real numbers, but operate on multiprecision binary or decimal integer values as well. A few examples, which show how the 80287 might be used in specific numerics applications, are described below. In many cases, these types of systems have been implemented in the past with minicomputers. The advent of the 80287 brings the size and cost savings of microprocessor technology to these applications for the first time. ~ Business data processingDDThe NPX's ability to accept decimal operands and produce exact decimal results of up to 18 digits greatly simplifies accounting programming. Financial calculations that use power functions can take advantage of the 80287's exponentiation and logarithmic instructions. ~ Process controlDDThe 80287 solves dynamic range problems automatically, and its extended precision allows control functions to be fine-tuned for more accurate and efficient performance. Control algorithms implemented with the NPX also contribute to improved reliability and safety, while the 80287's speed can be exploited in real-time operations. ~ Computer numerical control (CNC)DDThe 80287 can move and position machine tool heads with accuracy in real-time. Axis positioning also benefits from the hardware trigonometric support provided by the 80287. ~ RoboticsDDCoupling small size and modest power requirements with powerful computational abilities, the NPX is ideal for on-board six-axis positioning. ~ NavigationDDVery small, lightweight, and accurate inertial guidance systems can be implemented with the 80287. Its built-in trigonometric functions can speed and simplify the calculation of position from ~ Graphics terminalsDDThe 80287 can be used in graphics terminals to locally perform many functions that normally demand the attention of a main computer; these include rotation, scaling, and interpolation. By also using an 82720 Graphics Display Controller to perform high speed data transfers, very powerful and highly self-sufficient terminals can be built from a relatively small number of 80286 family parts. ~ Data acquisitionDDThe 80287 can be used to scan, scale, and reduce large quantities of data as it is collected, thereby lowering storage requirements and time required to process the data for analysis. The preceding examples are oriented toward traditional numerics applications. There are, in addition, many other types of systems that do not appear to the end user as computational, but can employ the 80287 to advantage. Indeed, the 80287 presents the imaginative system designer with an opportunity similar to that created by the introduction of the microprocessor itself. Many applications can be viewed as numerically-based if sufficient computational power is available to support this view. This is analogous to the thousands of successful products that have been built around "buried" microprocessors, even though the products themselves bear little resemblance to computers. Upgradability The architecture of the 80286 CPU is specifically adapted to allow easy upgradability to use an 80287, simply by plugging in the 80287 NPX. For this reason, designers of 80286 systems may wish to incorporate the 80287 NPX into their designs in order to offer two levels of price and performance at little additional cost. Two features of the 80286 CPU make the design and support of upgradable 80286 systems particularly simple: ~ The 80286 can be programmed to recognize the presence of an 80287 NPX; that is, software can recognize whether it is running on an 80286 or an 80287 system. ~ After determining whether the 80287 NPX is available, the 80286 CPU can be instructed to let the NPX execute all numeric instructions. If an 80287 NPX is not available, the 80286 CPU can emulate all 80287 numeric instructions in software. This emulation is completely transparent to the application softwareDDthe same object code may be used by both 80286 and 80287 systems. No relinking or recompiling of application software is necessary; the same code will simply execute faster on the 80287 than on the 80286 system. To facilitate this design of upgradable 80286 systems, Intel provides a software emulator for the 80287 that provides the functional equivalent of the 80287 hardware, implemented in software on the 80286. Except for timing, the operation of this 80287 emulator (E80287) is the same as for the 80287 NPX hardware. When the emulator is combined as part of the systems software, the 80286 system with 80287 emulation and the 80286 with 80287 hardware are virtually indistinguishable to an application program. This capability makes it easy for software developers to maintain a single set of programs for both systems. System manufacturers can offer the NPX as a simple plug-in performance option without necessitating any changes in the user's software. Programming Interface The 80286/80287 pair is programmed as a single processor; all of the 80287 registers appear to a programmer as extensions of the basic 80286 register set. The 80286 has a class of instructions known as ESCAPE instructions, all having a common format. These ESC instructions are numeric instructions for the 80287 NPX. These numeric instructions for the 80287 are simply encoded into the instruction stream along with 80286 instructions. All of the CPU memory-addressing modes may be used in programming the NPX, allowing convenient access to record structures, numeric arrays, and other memory-based data structures. All of the memory management and protection features of the CPU are extended to the NPX as well. Numeric processing in the 80287 centers around the NPX register stack. Programmers can treat these eight 80-bit registers as either a fixed register set, with instructions operating on explicitly-designated registers, or a classical stack, with instructions operating on the top one or two stack elements. Internally, the 80287 holds all numbers in a uniform 80-bit temporary-real format. Operands that may be represented in memory as 16-, 32-, or 64-bit integers, 32-, 64-, or 80-bit floating-point numbers, or 18-digit packed BCD numbers, are automatically converted into temporary-real format as they are loaded into the NPX registers. Computation results are subsequently converted back into one of these destination data formats when they are stored into memory from the NPX registers. Table 1-2 lists each of the seven data types supported by the 80287, showing the data format for each type. All operands are stored in memory with the least significant digits starting at the initial (lowest) memory address. Numeric instructions access and store memory operands using only this initial address. For maximum system performance, all operands should start at even memory addresses. Table 1-3 lists the 80287 instructions by class. No special programming tools are necessary to use the 80287, because all of the NPX instructions and data types are directly supported by the ASM286 Assembler and Intel's appropriate high-level languages. Software routines for the 80287 may be written in ASM286 Assembler or any of the following higher-level languages: PL/M-286 PASCAL-286 FORTRAN-286 C-286 In addition, all of the development tools supporting the 8086 and 8087 can also be used to develop software for the 80286 and 80287 operating in Real-Address mode. All of these high-level languages provide programmers with access to the computational power and speed of the 80287 without requiring an understanding of the architecture of the 80286 and 80287 chips. Such architectural considerations as concurrency and data synchronization are handled automatically by these high-level languages. For the ASM286 programmer, specific rules for handling these issues are discussed in a later section of this supplement. Table 1-2. Numeric Data Types Significant Data Type Bits Digits Approximate Range (Decimal) (Decimal) Word integer 16 4 -32,768 s X s +32,767 Short integer 32 9 -2*10^(9) s X s +2*10^(9) Long integer 64 18 -9*10^(18) s X s +9*10^(18) Packed decimal 80 18 -99...99 s X s +99...99 (18 digits) Short real 32 6-7 8.43*10^(-37) s 3X3 s 3.37*10^(38) Long real 64 15-16 4.19*10^(-307) s 3X3 s 1.67*10^(308) Temporary real 80 19 3.4*10^(-4932) s 3X3 s 1.2*10^(4932) Table 1-3. Principal NPX Instructions Class Instruction Types Data Transfer Load (all data types), Store (all data types), Exchange Arithmetic Add, Subtract, Multiply, Divide, Subtract Reversed, Divide Reversed, Square Root, Scale, Remainder, Integer Part, Change Sign, Absolute Value, Extract Comparison Compare, Examine, Test Transcendental Tangent, Arctangent, 2^(X) -1, Y*Log{2}(X+1), Y*Log{2}(X) Constants 0, 1, c, Log{10}2, Log{e}2, Log{2}10, Log2{e} Processor Load Control Word, Store Control Word, Store Status Word, Control Load Environment, Store Environment, Save, Restore, Clear Exceptions, Initialize, Set Protected Mode Hardware Interface As an extension of the 80286 processor, the 80287 is wired very much in parallel with the 80286 CPU. Four special status signals, PEREQ, PEACK, BUSY, and ERROR, permit the two processors to coordinate their activities. The 80287 NPX also monitors the 80286 S1, S0, COD/INTA, READY, HLDA, and CLK pins to monitor the execution of ESC instructions (numeric instructions) by the 80286. As shown in figure 1-2, the 80287 NPX is divided internally into two processing elements; the Bus Interface Unit (BIU) and the Numeric Execution Unit (NEU). The two units operate independently of one another: the BIU receives and decodes instructions, requests operand transfers with memory, and executes processor control instructions, whereas the NEU processes individual numeric instructions. The BIU handles all of the status and signal lines between the 80287 and the 80286. The NEU executes all instructions that involve the register stack. These instructions include arithmetic, logical, transcendental, constant, and data transfer instructions. The data path in the NEU is 84 bits wide (68 fraction bits, 15 exponent bits, and a sign bit), allowing internal operand transfers to be performed at very high speeds. The 80287 executes a single numeric instruction at a time. Before executing most ESC instructions, the 80286 tests the BUSY pin and, before initiating the command, waits until the 80287 indicates that it is not busy. Once initiated, the 80286 continues program execution, while the 80287 executes the numeric instruction. Unlike the 8087, which required a WAIT instruction to test the BUSY signal before each ESC opcode, these WAIT instructions are permissible, but not necessary, in 80287 programs. In all cases, a WAIT or ESC instruction should be inserted after any 80287 store to memory (except FSTSW or FSTCW) or load from memory (except FLDENV, FLDCW, or FRSTOR) before the 80286 reads or changes the memory value. When needed, all data transfers between memory and the 80287 NPX are performed by the 80286 CPU, using its Processor Extension Data Channel. Numeric data transfers performed by the 80286 use the same timing as any other bus cycle, and all such transfers come under the supervision of the 80286 memory management and protection mechanisms. The 80286 Processor Extension Data Channel and the hardware interface between the 80286 and 80287 processors are described in Chapter Six of the 80286 Hardware Reference Manual. From the programmer's perspective, the 80287 can be considered just an extension of the 80286 processor. All interaction between the 80286 and the 80287 processors on the hardware level is handled automatically by the 80286 and is transparent to the software. To communicate with the 80287, the 80286 uses the reserved I/O port addresses 00F8H, 00FAH, and 00FCH (I/O ports numbered 00F8H through 00FFH are reserved for the 80286/80287 interface). These I/O operations are performed automatically by the 80286 and are distinct from I/O operations that result from program I/O instructions. I/O operations resulting from the execution of ESC instructions are completely transparent to software. Any program may execute ESCAPE (numeric) instructions, without regard to its current I/O Privilege Level (IOPL). To guarantee correct operation of the 80287, programs must not perform any explicit I/O operations to any of the eight ports reserved for the 80287. The IOPL of the 80286 can be used to protect the integrity of 80287 computations in multiuser reprogrammable applications, preventing any accidental or other tampering with the 80287 (see Chapter Eight of the 80286 Operating System Writer's Guide). Figure 1-2. 80287 NPX Block Diagram Z D D D D D D D D D D DBD D D D D D D D D D D D D D D D D D D D D D D D D D ? BUS INTERFACE UNIT NUMERIC EXECUTION UNIT 3 3 3 ZDDDDDDDDDDDDDD? EXPONENT BUS   FRACTION BUS 3 3 CONTROL WORD 3 3 ZDDDDDDDDDD? : : ZDDDDDDDDDDDDD? 3 CDDDDDDDDDDDDDD4 3 EXPONENT 3MM:INTER-:MMM//PROGRAMMABLE// 3 3 STATUS WORD 3 3 3 MODULE 3 : FACE : // SHIFTER // 3 @DDDDDDDDDDDDDY @DDDDDDDDDDY :M/MM: @DDDDDDDDDDDDY 3 : 3 ZDDDDDDDDDDDD? : 16 :MMMMMMMMMMMM< 3 : NEU 3 MICROCODE 3 16 / :MMMMM; ZDDDDDDDDDDDD? 3 ZDDDDDDD?INSTRUCTION3CONTROL UNIT3 : / 68 H3 ARITHMETIC 3 3 3 FMMMMMMMMMM@DDDDDDDDDDDDYIMMMM9 :MMMMMM;3 MODULE 3 3 3 DATA 3 3 IMMMMMMM< 16 / / 64 :@DDDDDDDDDDDY 3 DataMMMMMM3 BUFFER 3 : ZDD? : :MMMM; HMMMMMM< 3 3 3 ZDDD3DDDDDD? : 3 Z?ZDDDDDDDDDDD? : ZDDDDDDDDDDD? 3 3 3MM3 OPERANDS 3< 3 3T33 3(7) HMM3 TEMPORARY 3 3 @DDDDDDDY 3 QUEUE 3 3 3A33 3 z 3 REGISTERS 3 3 :DDDDD? @DDD3DDDDDDY 3 3G33 3 z @DDDDDDDDDDDY 3 ZDDDDDDDD? 3 3 3 33 REGISTER 3 z 3 StatusMMM CONTROL 3 @DDDDDD3DDDDDDDDDDY 3W33 STACK 3 3 3 3 3O33 3 z 3 AddressMM UNIT 3 3 3R33 3 3 @DDDDDDDDDY 3D33D 80 BITS D3(0) 3 3 @DY@DDDDDDDDDDDDDY @ D D D D D D D D D D DAD D D D D D D D D D D D D D D D D D D D D D D D D D Y 80287 Numeric Processor Architecture To the programmer, the 80287 NPX appears as a set of additional registers complementing those of the 80286. These additional registers consist of ~ Eight individually-addressable 80-bit numeric registers, organized as a register stack ~ Three sixteen-bit registers containing: an NPX status word an NPX control word a tag word ~ Four 16-bit registers containing the NPX instruction and data pointers All of the NPX numeric instructions focus on the contents of these NPX registers. The NPX Register Stack The 80287 register stack is shown in figure 1-3. Each of the eight numeric registers in the 80287's register stack is 80 bits wide and is divided into fields corresponding to the NPX's temporary-real data type. Numeric instructions address the data registers relative to the register on the top of the stack. At any point in time, this top-of-stack register is indicated by the ST (Stack Top) field in the NPX status word. Load or push operations decrement ST by one and load a value into the new top register. A store-and-pop operation stores the value from the current ST register and then increments ST by one. Like 80286 stacks in memory, the 80287 register stack grows down toward lower-addressed registers. Many numeric instructions have several addressing modes that permit the programmer to implicitly operate on the top of the stack, or to explicitly operate on specific registers relative to the ST. The ASM286 Assembler supports these register addressing modes, using the expression ST(0), or simply ST, to represent the current Stack Top and ST(i) to specify the ith register from ST in the stack (0 s i s 7). For example, if ST contains 011B (register 3 is the top of the stack), the following statement would add the contents of the top two registers on the stack (registers 3 and 5): FADD ST, ST(2) The stack organization and top-relative addressing of the numeric registers simplify subroutine programming by allowing routines to pass parameters on the register stack. By using the stack to pass parameters rather than using "dedicated" registers, calling routines gain more flexibility in how they use the stack. As long as the stack is not full, each routine simply loads the parameters onto the stack before calling a particular subroutine to perform a numeric calculation. The subroutine then addresses its parameters as ST, ST(1), etc., even though ST may, for example, refer to physical register 3 in one invocation and physical register 5 in another. Figure 1-3. 80287 Register Set 80287 STACK: TAG FIELD 79 78 64 63 0 1 0 R1 IMMMMQMMMMMMMMQMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM; IMMMMMM; :SIGN3EXPONENT3 SIGNIFICAND : : : R2 GDDDDEDDDDDDDDEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD6 GDDDDDD6 R3 GDDDDEDDDDDDDDEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD6 GDDDDDD6 R4 GDDDDEDDDDDDDDEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD6 GDDDDDD6 R5 GDDDDEDDDDDDDDEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD6 GDDDDDD6 R6 GDDDDEDDDDDDDDEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD6 GDDDDDD6 R7 GDDDDEDDDDDDDDEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD6 GDDDDDD6 R8 GDDDDEDDDDDDDDEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD6 GDDDDDD6 HMMMMOMMMMMMMMOMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM< HMMMMMM< 15 0 IMMMMMMMMMMMMMMMMMMMMM; : CONTROL REGISTER : GDDDDDDDDDDDDDDDDDDDDD6 : STATUS REGISTER : GDDDDDDDDDDDDDDDDDDDDD6 : TAG WORD : GDDDDDDDDDDDDDDDDDDDDD6 : : GDINSTRUCTION POINTERD6 : : GDDDDDDDDDDDDDDDDDDDDD6 : : GD DATA POINTER D6 : : HMMMMMMMMMMMMMMMMMMMMM< The NPX Status Word The 16-bit status word shown in figure 1-4 reflects the overall state of the 80287. This status word may be stored into memory using the FSTSW/FNSTSW, FSTENV/FNSTENV, and FSAVE/FNSAVE instructions, and can be transferred into the 80286 AX register with the FSTSW AX/FNSTSW AX instructions, allowing the NPX status to be inspected by the CPU. The Busy bit (bit 15) and the BUSY pin indicate whether the 80287's execution unit is idle (B = 0) or is executing a numeric instruction or signalling an exception (B = 1). (The instructions FNSTSW, FNSTSW AX, FNSTENV, and FNSAVE do not set the Busy bit themselves, nor do they require the Busy bit to be clear in order to execute.) The four NPX condition code bits (C{0}-C{3}) are similar to the flags in a CPU: the 80287 updates these bits to reflect the outcome of arithmetic operations. The effect of these instructions on the condition code bits is summarized in table 1-4. These condition code bits are used principally for conditional branching. The FSTSWAX instruction stores the NPX status word directly into the CPU AX register, allowing these condition codes to be inspected efficiently by 80286 code. Bits 12-14 of the status word point to the 80287 register that is the current Stack Top (ST). The significance of the stack top has been described in the section on the Register Stack. Figure 1-4 shows the six error flags in bits 0-5 of the status word. Bit 7 is the error summary status (ES) bit. ES is set if any unmasked exception bits are set, and is cleared otherwise. If this bit is set, the ERROR signal is asserted. Bits 0-5 indicate whether the NPX has detected one of six possible exception conditions since these status bits were last cleared or reset. Table 1-4. Interpreting the NPX Condition Codes Instruction Type C{3} C{2} C{1} C{0} Interpretation Compare, Test 0 0 X X = value is not affected by instruction 0 ST ST = Top of stack > Source or 0 (FTST) 0 0 X X = value is not affected by instruction 1 ST ST = Top of stack < Source or 0 (FTST) 1 0 X X = value is not affected by instruction 0 ST ST = Top of stack = Source or 0 (FTST) 1 1 X X = value is not affected by instruction 1 ST ST = Top of stack is not comparable Remainder Q{1} Q{n} = Quotient bit n following complete reduction (C{2}=0) 0 Q{0} Q{n} = Quotient bit n following complete reduction (C{2}=0) Q{2} Q{n} = Quotient bit n following complete reduction (C{2}=0) Complete reduction with three low bits of quotient in C{0}, C{3}, and C{1} U U = value is undefined following instruction 1 U U = value is undefined following instruction U U = value is undefined following instruction Incomplete Reduction Examine 0 0 0 0 Valid, positive unnormalized 0 0 0 1 Invalid, positive, exponent = 0 0 0 1 0 Valid, negative, unnormalized 0 0 1 1 Invalid, negative, exponent = 0 0 1 0 0 Valid, positive, normalized 0 1 0 1 Infinity, positive 0 1 1 0 Valid, negative, normalized 0 1 1 1 Infinity, negative 1 0 0 0 Zero, positive 1 0 0 1 Empty Register 1 0 1 0 Zero, negative 1 0 1 1 Empty Register 1 1 0 0 Invalid, positive, exponent = 0 1 1 0 1 Empty Register 1 1 1 0 Invalid, negative, exponent = 0 1 1 1 1 Empty Register Figure 1-4. 80287 Status Word 15 0 IMQMMQMMMQMMQMMQMMQMMQMQMMQMMQMMQMMQMMQMM; EXCEPTION FLAGS :B3C33S T3C23C13C03ES3X3PE3UE3OE3ZE3DE3IE: (1 = EXCEPTION HQOMQOQQQOMQOMQOMQOMQOQOMQOMQOMQOMQOMQOMQ< HAS OCCURRED) 3 3 333 3 3 3 3 3 3 3 3 3 3 @DDDDDDDDDDD INVALID OPERATION For definitions, see the section on exception handling. 3 3 333 3 3 3 3 3 3 3 3 3 @DDDDDDDDDDDDDD DENORMALIZED OPERAND For definitions, see the section on exception handling. 3 3 333 3 3 3 3 3 3 3 3 @DDDDDDDDDDDDDDDDD ZERO DIVIDE For definitions, see the section on exception handling. 3 3 333 3 3 3 3 3 3 3 @DDDDDDDDDDDDDDDDDDDD OVERFLOW For definitions, see the section on exception handling. 3 3 333 3 3 3 3 3 3 @DDDDDDDDDDDDDDDDDDDDDDD UNDERFLOW For definitions, see the section on exception handling. 3 3 333 3 3 3 3 3 @DDDDDDDDDDDDDDDDDDDDDDDDDD PRECISION For definitions, see the section on exception handling. 3 3 333 3 3 3 3 @DDDDDDDDDDDDDDDDDDDDDDDD (RESERVED) 3 3 333 3 3 3 @DDDDDDDDDDDDDDDDDDDDDDDDDD ERROR SUMMARY STATUS ES is set if any unmasked exception bit is set, cleared or otherwise. 3 @D333DDADDADDADDDDDDDDDDDDDDDDDDDDDDDDDDDDD CONDITION CODE See Table 1-4 for condition code interpretation. 3 @AADDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD STACK TOP POINTER S T VALUES: 000 = REGISTER 0 IS TOP OF STACK 001 = REGISTER 1 IS TOP OF STACK y y y y 111 = REGISTER 7 IS TOP OF STACK @DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD NEU BUSY Control Word The NPX provides the programmer with several processing options, which are selected by loading a word from memory into the control word. Figure 1-5 shows the format and encoding of the fields in the control word. The low-order byte of this control word configures the 80287 error and exception masking. Bits 0-5 of the control word contain individual masks for each of the six exception conditions recognized by the 80287. The high-order byte of the control word configures the 80287 processing options, including ~ Precision control ~ Rounding control ~ Infinity control The Precision control bits (bits 8-9) can be used to set the 80287 internal operating precision at less than the default precision (64-bit significand). These control bits can be used to provide compatibility with the earlier-generation arithmetic processors having less precision than the 80287, as required by the IEEE 754 standard. Setting a lower precision, however, will not affect the execution time of numeric calculations. The rounding control bits (bits 10-11) provide for directed rounding and true chop as well as the unbiased round-to-nearest-even mode specified in the IEEE 754 standard. The infinity control bit (bit 12) determines the manner in which the 80287 treats the special values of infinity. Either affine closure (where positive infinity is distinct from negative infinity) or projective closure (infinity is treated as a single unsigned quantity) may be specified. These two alternative views of infinity are discussed in the section on Computation Fundamentals. Figure 1-5. 80287 Control Word Format IMMMMMQMMMQMMMQMMMQMQMQMMQMMQMMQMMQMMQMM; :X X X3I C3R C3P C3X3X3PM3UM3OM3ZM3DM3IM: EXCEPTION MASKS HQMQMQOMQMOQMQOQMQOQOQOMQOMQOMQOMQOMQOMQ< (1 = EXCEPTION IS MASKED) 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 @DDDD INVALID OPERATION 3 3 3 3 3 3 3 3 3 3 3 3 3 3 @DDDDDDD DENORMALIZED OPERAND 3 3 3 3 3 3 3 3 3 3 3 3 3 @DDDDDDDDDD ZERO DIVIDE 3 3 3 3 3 3 3 3 3 3 3 3 @DDDDDDDDDDDDD OVERFLOW 3 3 3 3 3 3 3 3 3 3 3 @DDDDDDDDDDDDDDDD UNDERFLOW 3 3 3 3 3 3 3 3 3 3 @DDDDDDDDDDDDDDDDDDD PRECISION 3 3 3 3 3 3 3 3 3 @DDDDDDDDDDDDDDDDDDDDDD (RESERVED) 3 3 3 3 3 3 3 3 @DDDDDDDDDDDDDDDDDDDDDDDD (RESERVED) 3 3 3 3 3 3 @DADDDDDDDDDDDDDDDDDDDDDDDDDD PRECISION CONTROL PRECISION CONTROL 00 = 24-BIT SIGNIFICAND 01 = RESERVED 10 = 53-BIT SIGNIFICAND 11 = 64-BIT SIGNIFICAND 3 3 3 3 @DADDDDDDDDDDDDDDDDDDDDDDDDDDDDDD ROUNDING CONTROL ROUNDING CONTROL 00 = ROUND TO NEAREST OR EVEN 01 = ROUND DOWN (TOWARD -l) 10 = ROUND UP (TOWARD +l) 11 = CHOP (TRUNCATE TOWARD ZERO) 3 3 3 @DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD INFINITY CONTROL 3 3 3 (0 = PROJECTIVE, 1 = AFFINE) @DADADDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD (RESERVED) The NPX Tag Word The tag word indicates the contents of each register in the register stack, as shown in figure 1-6. The tag word is used by the NPX itself in order to track its numeric registers and optimize performance. Programmers may use this tag information to interpret the contents of the numeric registers. The tag values are stored in the tag word corresponding to the physical registers 0-7. Programmers must use the current Stack Top (ST) pointer stored in the NPX status word to associate these tag values with the relative stack registers ST(0) through ST(7). Figure 1-6. 80287 Tag Word Format 15 0 IMMMMMMMMQMMMMMMMMQMMMMMMMMQMMMMMMMMQMMMMMMMMQMMMMMMMMQMMMMMMMMQMMMMMMMM; : TAG(7) 3 TAG(6) 3 TAG(5) 3 TAG(4) 3 TAG(3) 3 TAG(2) 3 TAG(1) 3 TAG(0) : HMMMMMMMMOMMMMMMMMOMMMMMMMMOMMMMMMMMOMMMMMMMMOMMMMMMMMOMMMMMMMMOMMMMMMMM< TAG VALUES: 00 = VALID; 01 = ZERO; 10 = INVALID OR INFINITY; 11 = EMPTY The NPX Instruction and Data Pointers The NPX instruction and data registers provide support for programmed exception-handlers. Whenever the 80287 executes a math instruction, the NPX internally saves the instruction address, the operand address (if present), and the instruction opcode. The 80287 FSTENV and FSAVE instructions store this data into memory, allowing exception handlers to determine the precise nature of any numeric exceptions that may be encountered. When stored in memory, the instruction and data pointers appear in one of two formats, depending on the operating mode of the 80287. Figure 1-7 shows these pointers as they are stored following an FSTENV instruction. In Real-Address mode, these values are the 20-bit physical address and 11-bit opcode formatted like the 8087. In Protected mode, these values are the 32-bit virtual addresses used by the program that executed the ESC instruction. The instruction address saved in the 80287 will point to any prefixes that preceded the instruction. This is different from the 8087, for which the instruction address pointed only to the ESC instruction opcode. Figure 1-7. 80287 Instruction and Data Pointer Image in Memory MEMORY OFFSET IMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM; REAL MODE : CONTROL WORD : +0 GDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD6 : STATUS WORD : +2 GDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD6 : TAG WORD : +4 GDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD6 : INSTRUCTION POINTER(15-0) : +6 GDDDDDDDDDDDBDBDDDDDDDDDDDDDDDDD6 :INSTRUCTION3 3 INSTRUCTION : : POINTER 303 OPCODE : +8 : (19-16) 3 3 (10-0) : GDDDDDDDDDDDADADDDDDDDDDDDDDDDDD6 : DATA POINTER(15-0) : +10 GDDDDDDDDDDDBDDDDDDDDDDDDDDDDDDD6 : DATA 3 : : POINTER 3 0 : +12 : (19-16) 3 : HMMMMMMMMMMMOMMMMMMMMMMMMMMMMMMM< 15 12 11 0 MEMORY OFFSET IMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM; PROTECTED MODE : CONTROL WORD : +0 GDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD6 : STATUS WORD : +2 GDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD6 : TAG WORD : +4 GDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD6 : IP OFFSET : +6 GDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD6 : CS SELECTOR : +8 GDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD6 : DATA OPERAND OFFSET : +10 GDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD6 : DATA OPERAND SELECTOR : +12 HMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM< 15 0 Computation Fundamentals This section covers 80287 programming concepts that are common to all applications. It describes the 80287's internal number system and the various types of numbers that can be employed in NPX programs. The most commonly used options for rounding, precision, and infinity (selected by fields in the control word) are described, with exhaustive coverage of less frequently used facilities deferred to later sections. Exception conditions that may arise during execution of NPX instructions are also described along with the options that are available for responding to these exceptions. Number System The system of real numbers that people use for pencil and paper calculations is conceptually infinite and continuous. There is no upper or lower limit to the magnitude of the numbers one can employ in a calculation, or to the precision (number of significant digits) that the numbers can represent. When considering any real number, there is always an infinity of numbers both larger and smaller. There is also an infinity of numbers between (i.e., with more significant digits than) any two real numbers. For example, between 2.5 and 2.6 are 2.51, 2.5897, 2.500001, etc. While ideally it would be desirable for a computer to be able to operate on the entire real number system, in practice this is not possible. Computers, no matter how large, ultimately have fixed-size registers and memories that limit the system of numbers that can be accommodated. These limitations determine both the range and the precision of numbers. The result is a set of numbers that is finite and discrete, rather than infinite and continuous. This sequence is a subset of the real numbers that is designed to form a useful approximation of the real number system. Figure 1-8 superimposes the basic 80287 real number system on a real number line (decimal numbers are shown for clarity, although the 80287 actually represents numbers in binary). The dots indicate the subset of real numbers the 80287 can represent as data and final results of calculations. The 80287's range is approximately q4.19*10^(-307) to q1.67*10^(308). Applications that are required to deal with data and final results outside this range are rare. For reference, the range of the IBM 370 is about q0.54*10^(-78) to q0.72*10^(76). The finite spacing in figure 1-8 illustrates that the NPX can represent a great many, but not all, of the real numbers in its range. There is always a gap between two adjacent 80287 numbers, and it is possible for the result of a calculation to fall in this space. When this occurs, the NPX rounds the true result to a number that it can represent. Thus, a real number that requires more digits than the 80287 can accommodate (e.g., a 20-digit number) is represented with some loss of accuracy. Notice also that the 80287's representable numbers are not distributed evenly along the real number line. In fact, an equal number of representable numbers exists between successive powers of 2 (i.e., as many representable numbers exist between 2 and 4 as between 65,536 and 131,072). Therefore, the gaps between representable numbers are larger as the numbers increase in magnitude. All integers in the range q2^(64) (approximately q10^(18)), however, are exactly representable. In its internal operations, the 80287 actually employs a number system that is a substantial superset of that shown in figure 1-8. The internal format (called temporary real) extends the 80287's range to about q3.4*10^(-4932) to q1.2*10^(4932), and its precision to about 19 (equivalent decimal) digits. This format is designed to provide extra range and precision for constants and intermediate results, and is not normally intended for data or final results. From a practical standpoint, the 80287's set of real numbers is sufficiently large and dense so as not to limit the vast majority of microprocessor applications. Compared to most computers, including mainframes, the NPX provides a very good approximation of the real number system. It is important to remember, however, that it is not an exact representation, and that arithmetic on real numbers is inherently approximate. Conversely, and equally important, the 80287 does perform exact arithmetic on integer operands. That is, an operation on two integers returns an exact integral result, provided that the true result is an integer and is in range. For example, 4 v 2 yields an exact integer, 1 v 3 does not, and 2^(40) * 2^(30) + 1 does not, because the result requires greater than 64 bits of precision. Figure 1-8. 80287 Number System |DDDNEGATIVE RANGE (NORMALIZED)DD| | | | -5 -4 -3 -2 -1 | ZDDDBDDDBD?ZDDDBDDDBDDDBDDDBDDDBDDD? 3 3 3 3300030003111311132223[[[3 @DDDADDDADY@DDDADDDADDDADDDADDDADDDY   3 3 ZDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD? @-1.67*10^(308) -4.19*10^(-307)Y 3 DDDDDDDDDDDDBDDDDDDDDDDDDDD 3 3 222222222222311111111111111 3 3 222222222222311111111111111 3 |DDDPOSITIVE RANGE (NORMALIZED)DD| 3 DDDDDDDDDDDDDDDDDDDDDDDD 3 | | 3   3 | 1 2 3 4 5 | 3 3DDBDD3 3 ZDDDBDDDBDDDBDDDBDDDBDDD?ZDBDDDBDDD? 3 3 3 @ 2.00000000000000000 3 3[[[3222311131113000300033 3 3 3 3 3 3 3 @DDDADDDADDDADDDADDDADDDY@DADDDADDDY 3 3 @DDDD (NOT REPRESENTABLE) 3  @DBDY  3 3 3 3 @DDDDDDDD? 3 3 @DDDDDDDD 1.99999999999999999 3 3 3 1.67*10^(308)Y 3 PRECISION: 3DD 18 DIGITS DD3 3 @4.19*10^(-307) @DDDDDDDDDDDDDDDDDDDDDADDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDY Data Types and Formats The 80287 recognizes seven numeric data types, divided into three classes: binary integers, packed decimal integers, and binary reals. A later section describes how these formats are stored in memory (the sign is always located in the highest-addressed byte). Figure 1-9 summarizes the format of each data type. In the figure, the most significant digits of all numbers (and fields within numbers) are the leftmost digits. Table 1-5 provides the range and number of signficant (decimal) digits that each format can accommodate. Table 1-5. Real Number Notation ZDDDDDDDDDDDDDDDDDDDBDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD? 3 Notation 3 Value 3 CDDDDDDDDDDDDDDDDDDDEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD4 3Ordinary Decimal 3 178.125 3 CDDDDDDDDDDDDDDDDDDDEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD4 3Scientific Decimal 3 1{}78125E2 3 CDDDDDDDDDDDDDDDDDDDEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD4 3Scientific Binary 3 1{)0110010001E111 3 CDDDDDDDDDDDDDDDDDDDEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD4 3Scientific Binary 3 1{}0110010001E10000110 3 3(Biased Exponent) 3 3 CDDDDDDDDDDDDDDDDDDDEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD4 3 3 Sign Biased Exponent Significand 3 3 CDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD4 380287 Short Real 3 3 3(Normalized) 3 0 10000110  01100100010000000000000 3 3 3 @DDDD1{}(implicit) 3 @DDDDDDDDDDDDDDDDDDDADDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDY Figure 1-9. Data Formats DDDDDDDD INCREASING SIGNIFICANCE IMQMMMMMMMMM; WORD :S3MAGNITUDE: (TWO'S INTEGER HMOMMMMMMMMM< COMPLEMENT) 15 0 IMQMMMMMMMMMMMMMMMMMMMMMM; SHORT :S3 MAGNITUDE : (TWO'S INTEGER HMOMMMMMMMMMMMMMMMMMMMMMM< COMPLEMENT) 31 0 IMQMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM; LONG :S3 MAGNITUDE : (TWO'S INTEGER HMOMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM< COMPLEMENT) 63 0 IMQMMMQMMMMMMMMMMMMMMMMMMMMMMMMMAGNITUDEMMMMMMMMMMMMMMMMMMMMMMMM; PACKED :S3 X 3d17 d16    d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0: DECIMAL HMOMMMOMMMOMMMOMMMMMMMMMMMOMMMOMMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMM< 79 72 0 IMQMMMMMMMMQMMMMMMMMMMMMM; SHORT :S3 BIASED 3 SIGNIFICAND : REAL : 3EXPONENT3 : HMOMMMMMMM Position of implicit binary point. Integer bit of significand; stored in temporary real, implicit (always 1) in short and long real MMMMMMMMMMMM< 31 22 0 IMQMMMMMMMMMMMMQMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM; LONG :S3 BIASED 3 SIGNIFICAND : REAL : 3 EXPONENT 3 : HMOMMMMMMMMMMM Position of implicit binary point. Integer bit of significand; stored in temporary real, implicit (always 1) in short and long real MMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM< 63 51 0 IMQMMMMMMMMMMMMMQMQMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM; TEMPORARY :S3 BIASED 313 SIGNIFICAND : REAL : 3 EXPONENT 3 3 : HMOMMMMMMMMMMMMMO Position of implicit binary point MMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM< 79 64 63 0 NOTES: S = Sign bit (0 = positive, 1 = negative) dn = Decimal digit (two per byte) X = Bits have no significance; 80287 ignores when loading, zeros when storing. Exponent Bias (normal values): Short Real: 127 (7FH) Long Real: 1023 (3FFH) Temporary Real: 16383 (3FFFH) Binary Integers The three binary integer formats are identical except for length, which governs the range that can be accommodated in each format. The leftmost bit is interpreted as the number's sign: 0 = positive and 1 = negative. Negative numbers are represented in standard two's complement notation (the binary integers are the only 80287 format to use two's complement). The quantity zero is represented with a positive sign (all bits are 0). The 80287 word integer format is identical to the 16-bit signed integer data type of the 80286. Decimal Integers Decimal integers are stored in packed decimal notation, with two decimal digits "packed" into each byte, except the leftmost byte, which carries the sign bit (0 = positive, 1 = negative). Negative numbers are not stored in two's complement form and are distinguished from positive numbers only by the sign bit. The most significant digit of the number is the leftmost digit. All digits must be in the range 0H-9H. Real Numbers The 80287 stores real numbers in a three-field binary format that resembles scientific, or exponential, notation. The number's significant digits are held in the significand field, the exponent field locates the binary point within the significant digits (and therefore determines the number's magnitude), and the sign field indicates whether the number is positive or negative. (The exponent and significand are analogous to the terms "characteristic" and "mantissa" used to describe floating point numbers on some computers.) Negative numbers differ from positive numbers only in the sign bits of their significands. Table 1-5 shows how the real number 178.125 (decimal) is stored in the 80287 short real format. The table lists a progression of equivalent notations that express the same value to show how a number can be converted from one form to another. The ASM286 and PL/M-286 language translators perform a similar process when they encounter programmer-defined real number constants. Note that not every decimal fraction has an exact binary equivalent. The decimal number 1/10, for example, cannot be expressed exactly in binary (just as the number 1/3 cannot be expressed exactly in decimal). When a translator encounters such a value, it produces a rounded binary approximation of the decimal value. The NPX usually carries the digits of the significand in normalized form. This means that, except for the value zero, the significand is an integer and a fraction as follows: 1{}fff...ff where  indicates an assumed binary point. The number of fraction bits varies according to the real format: 23 for short, 52 for long, and 63 for temporary real. By normalizing real numbers so that their integer bit is always a 1, the 80287 eliminates leading zeros in small values (3X3 < 1). This technique maximizes the number of significant digits that can be accommodated in a significand of a given width. Note that, in the short and long real formats, the integer bit is implicit and is not actually stored; the integer bit is physically present in the temporary real format only. If one were to examine only the signficand with its assumed binary point, all normalized real numbers would have values between 1 and 2. The exponent field locates the actual binary point in the significant digits. Just as in decimal scientific notation, a positive exponent has the effect of moving the binary point to the right, and a negative exponent effectively moves the binary point to the left, inserting leading zeros as necessary. An unbiased exponent of zero indicates that the position of the assumed binary point is also the position of the actual binary point. The exponent field, then, determines a real number's magnitude. In order to simplify comparing real numbers (e.g., for sorting), the 80287 stores exponents in a biased form. This means that a constant is added to the true exponent described above. The value of this bias is different for each real format (see figure 1-9). It has been chosen so as to force the biased exponent to be a positive value. This allows two real numbers (of the same format and sign) to be compared as if they are unsigned binary integers. That is, when comparing them bitwise from left to right (beginning with the leftmost exponent bit), the first bit position that differs orders the numbers; there is no need to proceed further with the comparison. A number's true exponent can be determined simply by subtracting the bias value of its format. The short and long real formats exist in memory only. If a number in one of these formats is loaded into an 80287 register, it is automatically converted to temporary real, the format used for all internal operations. Likewise, data in registers can be converted to short or long real for storage in memory. The temporary real format may be used in memory also, typically to store intermediate results that cannot be held in registers. Most applications should use the long real form to store real number data and results; it provides sufficient range and precision to return correct results with a minimum of programmer attention. The short real format is appropriate for applications that are constrained by memory, but it should be recognized that this format provides a smaller margin of safety. It is also useful for debugging algorithms, because roundoff problems will manifest themselves more quickly in this format. The temporary real format should normally be reserved for holding intermediate results, loop accumulations, and constants. Its extra length is designed to shield final results from the effects of rounding and overflow/underflow in intermediate calculations. However, the range and precision of the long real form are adequate for most microcomputer applications. Rounding Control Internally, the 80287 employs three extra bits (guard, round, and sticky bits) that enable it to represent the infinitely precise true result of a computation; these bits are not accessible to programmers. Whenever the destination can represent the infinitely precise true result, the 80287 delivers it. Rounding occurs in arithmetic and store operations when the format of the destination cannot exactly represent the infinitely precise true result. For example, a real number may be rounded if it is stored in a shorter real format, or in an integer format. Or, the infinitely precise true result may be rounded when it is returned to a register. The NPX has four rounding modes, selectable by the RC field in the control word (see figure 1-5). Given a true result b that cannot be represented by the target data type, the 80287 determines the two representable numbers a and c that most closely bracket b in value (a < b < c). The processor then rounds (changes) b to a or to c according to the mode selected by the RC field as shown in table 1-6. Round introduces an error in a result that is less than one unit in the last place to which the result is rounded. "Round to nearest" is the default mode and is suitable for most applications; it provides the most accurate and statistically unbiased estimate of the true result. The chop mode is provided for integer arithmetic applications. "Round up" and "round down" are termed directed rounding and can be used to implement interval arithmetic. Interval arithmetic generates a certifiable result independent of the occurrence of rounding and other errors. The upper and lower bounds of an interval may be computed by executing an algorithm twice, rounding up in one pass and down in the other. Table 1-6. Rounding Modes ZDDDDDDDDBDDDDDDDDDDDDDDDDDDDDDDDDBDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD? 3RC Field3 Rounding Mode 3 Rounding Action 3 CDDDDDDDDEDDDDDDDDDDDDDDDDDDDDDDDDEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD4 3 00 3 Round to nearest 3 Closer to b of a or c; if equally 3 3 3 3 close, select even number (the one 3 3 3 3 whose least significant bit is zero). 3 3 3 3 3 3 01 3 Round down (toward -l) 3 a 3 3 3 3 3 3 10 3 Round up (toward +l) 3 c 3 3 3 3 3 3 11 3 Chop (toward 0) 3 Smaller in magnitude of a or c 3 @DDDDDDDDADDDDDDDDDDDDDDDDDDDDDDDDADDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDY DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD NOTE a < b < c; a and c are representable, b is not. DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD Precision Control The 80287 allows results to be calculated with either 64, 53, or 24 bits of precision in the significand as selected by the precision control (PC) field of the control word. The default setting, and the one that is best suited for most applications, is the full 64 bits of significance provided by the temporary-real format. The other settings are required by the proposed IEEE standard, and are provided to obtain compatibility with the specifications of certain existing programming languages. Specifying less precision nullifies the advantages of the temporary real format's extended fraction length, and does not increase execution speed. When reduced precision is specified, the rounding of the fractional value clears the unused bits on the right to zeros. Infinity Control The 80287's system of real numbers may be closed by either of two models of infinity. These two means of closing the number system, projective and affine closure, are illustrated schematically in figure 1-10. The setting of the IC field in the control word selects one model or the other. The default means of closure is projective, and this is recommended for most computations. When projective closure is selected, the NPX treats the special values +l and -l as a single unsigned infinity (similar to its treatment of signed zeros). In the affine mode the NPX respects the signs of +l and -l. While affine mode may provide more information than projective, there are occasions when the sign may in fact represent misinformation. For example, consider an algorithm that yields an intermediate result x of +0 and -0 (the same numeric value) in different executions. If 1/x were then computed in affine mode, two entirely different values (+l and -l) would result from numerically identical values of x. Projective mode, on the other hand, provides less information but never returns misinformation. In general, then, projective mode should be used globally, with affine mode reserved for local computations where the programmer can take advantage of the sign and knows for certain that the nature of the computations will not produce a misleading result. Figure 1-10. Projective versus Affine Closure PROJECTIVE CLOSURE AFFINE CLOSURE l ZDDDDDDDD? 3 3 - 3 3 + -l - + +l 3 3 DDDDDDDDDDEDDDDDDDDDD @DDDDDEDDDDDY 0 0 Special Computational Situations Besides being able to represent positive and negative numbers, the 80287 data formats may be used to describe other entities. These special values provide extra flexibility, but most users will not need to understand them in order to use the 80287 successfully. This section describes the special values that may occur in certain cases and the significance of each. The 80286 exceptions are also described, for writers of exception handlers and for those interested in probing the limits of computation using the 80287. The material presented in this section is mainly of interest to programmers concerned with writing exception handlers. For many readers, this section can be browsed lightly. Special Numeric Values The 80287 data formats encompass encodings for a variety of special values in addition to the typical real or integer data values that result from normal calculations. These special values have significance and can express relevant information about the computations or operations that produced them. The various types of special values are ~ Non-normal real numbers, including denormals unnormals ~ Zeros and pseudo zeros ~ Positive and negative infinity ~ NaN (Not-a-Number) ~ Indefinite The following description explains the origins and significance of each of these special values. Tables 1-12 through 1-15 at the end of this section show how each of these special values is encoded for each of the numeric data types. Nonnormal Real Numbers As described previously, the 80287 generally stores nonzero real numbers in normalized floating-point form; that is, the integer (leading) bit of the significand is always a 1. This bit is explicitly stored in the temporary real format, and is implicitly assumed to be a one (1{}) in the short- and long-real formats. Since leading zeros are eliminated, normalized storage allows the maximum number of significant digits to be held in a significand of a given width. When a floating-point numeric value becomes very close to zero, normalized storage cannot be used to express the value accurately. To accommodate these instances, the 80287 can store and operate on reals that are not normalized, i.e., whose significands contain one or more leading zeros. Nonnormals typically arise when the result of a calculation yields a value that is too small to be represented in normal form. Nonnormal values can exist in one of two forms: ~ The floating-point exponent may be stored at its most negative value (a Denormal), ~ The integer bit (and perhaps other leading bits) of the significand may be zero (an Unnormal). The leading zeros of nonnormals permit smaller numbers to be represented, at the cost of some lost precision (the number of significant bits is reduced by the leading zeros). In typical algorithms, extremely small values are most likely to be generated as intermediate, rather than final results. By using the NPX's temporary real format for holding intermediate, values as small as q3.4*10^(-4932) can be represented; this makes the occurrence of nonnormal numbers a rare phenomenon in 80287 applications. Nevertheless, the NPX can load, store, and operate on nonnormalized real numbers when they do occur. Denormals and Gradual Underflow A denormal is the result of the NPX's response to an underflow exception when that exception has been masked by the programmer (see the 80287 control word, figure 1-5). Underflow occurs when the absolute value of a real number becomes too small to be represented in the destination format, that is, when the exponent of the true result is too negative to be represented in the destination format. For example, a true exponent of -130 will cause underflow if the destination is short real, because -126 is the smallest exponent this format can accommodate. No underflow would occur if the destination were long real or temporary real, since these formats can handle exponents down to -1023 and -16,383, respectively. Most computers underflow "abruptly:" they simply return a zero result, which is likely to produce an unacceptable final result if computation continues. The 80287, on the other hand, underflows "gradually" when the underflow exception is masked. Gradual underflow is accomplished by denormalizing the result until it is just within the exponent range of the destination format. Denormalizing means incrementing the true result's exponent and inserting a corresponding leading zero in the significand, shifting the rest of the significand one place to the right. Denormal values may occur in any of the short-real, long-real, or temporary-real formats. Table 1-7 illustrates how a result might be denormalized to fit a short-real destination. The intent of the 80287's masked response to underflow is to allow computation to continue without program intervention, while introducing an error that carries about the same risk of contaminating the final result as roundoff error. Roundoff (precision) errors occur frequently in real number calculations; sometimes they spoil the result of computation, but often they do not. Recognizing that roundoff errors are often nonfatal, computation usually proceeds, and the programmer inspects the final results to see if these errors have had a significant effect. The 80287's masked underflow response allows programmers to treat underflows in a similar manner; the computation continues and the programmer can examine the final result to determine if an underflow has had important consequences. (If the underflow has had a significant effect, an invalid operation will probably be signalled later in the computation.) Denormalization produces a denormal or a zero. Denormals are readily identified by their exponents, which are always the minimum for their formats; in biased form, this is always the bit string: 00...00. This same exponent value is also assigned to the zeros, but a denormal has a nonzero significand. A denormal in a register is tagged special. Tables 1-14 and 1-15 later in this chapter show how denormal values are encoded in each of the real data formats. The denormalization process may cause the loss of low-order significand bits as they are shifted off the right. In a severe case, all the significand bits of the true result are shifted out and replaced by the leading zeros. In this case, the result of denormalization is a true zero, and if the value is in a register, it is tagged as such. However, this is a comparatively rare occurrence and, in any case, is no worse than "abrupt" underflow. Denormals are rarely encountered in most applications. Typical debugged algorithms generate extremely small results during the evaluation of intermediate subexpressions; the final result is usually of an appropriate magnitude for its short or long real destination. If intermediate results are held in temporary real, as is recommended, the great range of this format makes underflow very unlikely. Denormals are likely to arise only when an application generates a great many intermediates, so many that they cannot be held on the register stack or in temporary real memory variables. If storage limitations force the use of short or long reals for intermediates, and small values are produced, underflow may occur, and, if masked, may generate denormals. Accessing a denormal may produce an exception as shown in table 1-8. (The denormalized exception signals that a denormal has been fetched.) Denormals may have reduced significance due to lost low-order bits, and an option of the proposed IEEE standard precludes operations on nonnormalized operands. This option may be implemented in the form of an exception handler that responds to unmasked denormalized exceptions. Most users will mask this exception so that computation may proceed; any loss of accuracy will be analyzed by the user when the final result is delivered. As table 1-8 shows, the division and remainder operations do not accept denormal divisors and raise the invalid operation exception. Recall also that the transcendental instructions require normalized operands and do not check for exceptions. In all other cases, the NPX converts denormals to unnormals, and the rules governing unnormal arithmetic then apply (unnormals are described in the following section). Table 1-7. Denormalization Process ZDDDDDDDDDDDDDDDDDDBDDDDDDDDBDDDDDDDDDDDDBDDDDDDDDDDDDDDDDDDDDDDDDDDD? 3Operation 3 Sign 3 Exponent Expressed as unbiased, decimal number 3 Significand 3 3DDDDDDDDDDDDDDDDDDEDDDDDDDDEDDDDDDDDDDDDEDDDDDDDDDDDDDDDDDDDDDDDDDDD4 3True Result 3 0 3 -129 3 1{}01011100...00 3 3Denormalize 3 0 3 -128 3 0{}101011100...00 3 3Denormalize 3 0 3 -127 3 0{}0101011100...00 3 3Denormalize 3 0 3 -126 3 0{}00101011100...00 3 3Denormal Result Before storing, significand is rounded to 24 bits, integer bit is dropped, and exponent is biased by adding 126 3 0 3 -126 3 0{}00101011100...00 3 @DDDDDDDDDDDDDDDDDDADDDDDDDDADDDDDDDDDDDDADDDDDDDDDDDDDDDDDDDDDDDDDDDY Table 1-8. Exceptions Due to Denormal Operands ZDDDDDDDDDDDDDDDDDDDDDDDDDDDDDBDDDDDDDDDDDBDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD? 3Operation 3 Exception 3 Masked Response 3 CDDDDDDDDDDDDDDDDDDDDDDDDDDDDDEDDDDDDDDDDDEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD4 3FLD (short/long real) 3 D 3 Load as equivalent unnormal 3 CDDDDDDDDDDDDDDDDDDDDDDDDDDDDDEDDDDDDDDDDDEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD4 3Arithmetic (except following)3 D 3 Convert (in a work area) 3 3 3 3 denormal to equivalent 3 3 3 3 unnormal and proceed 3 CDDDDDDDDDDDDDDDDDDDDDDDDDDDDDEDDDDDDDDDDDEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD4 3Compare and test 3 D 3 Convert (in a work area) 3 3 3 3 denormal to equivalent 3 3 3 3 unnormal and proceed 3 CDDDDDDDDDDDDDDDDDDDDDDDDDDDDDEDDDDDDDDDDDEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD4 3Division or FPREM with 3 I 3 Return real indefinite 3 3denormal divisor 3 3 3 @DDDDDDDDDDDDDDDDDDDDDDDDDDDDDADDDDDDDDDDDADDDDDDDDDDDDDDDDDDDDDDDDDDDDDDY UnnormalsDDDescendents of Denormal Operands An unnormal is the result of a computation using denormal operands and is therefore the descendent of the 80287's masked underflow response. An unnormal may exist only in the temporary real format; it may have any exponent that a normal value may have (that is, in biased form any nonzero value), but it is distinguished from a normal by the integer bit of its significand, which is always 0. An unnormal in a register is tagged valid. Unnormals are distinct from denormals, which have an exponent of 00...00 in biased form. Unnormals allows arithmetic to continue following an underflow while still retaining their identity as numbers that may have reduced significance. That is, unnormal operands generate unnormal results, so long as their unnormality has a significant effect on the result. Unnormals are thus prevented from "masquerading" as normals, numbers that have full significance. On the other hand, if an unnormal has an insignificant effect on a calculation with a normal, the result will be normal. For example, adding a small unnormal to a large normal yields a normal result. The converse situation yields an unnormal. Table 1-9 shows how the instruction set deals with unnormal operands. Note that the unnormal may be the original operand or a temporary created by the 80287 from a denormal. Table 1-9. Unnormal Operands and Results Operation Result Addition/subtraction Normalization of operand with larger abosolute value determines normalization of result. Multiplication If either operand is unnormal, result is unormal. Division (unnormal dividend only) Result is unnormal. FPREM (unnormal dividend only) Result if normalized. Division/FPREM (unnormal Signal invalid operation. divisor) Compare/FTST Normalize as much as possible before making comparison. FRNDINT Normalize as much as possible before rounding. FSQRT Signal invalid operation. FST, FSTP (short/long real If value is above destination's underflow destination) boundary, then signal invalid operation; else signal underflow. FSTP (temporary real destination) Store as usual. FIST, FISTP, FBSTP Signal invalid operation. FLD Load as usual. FXCH Exchange as usual. Transcendental instructions Undefined; operands must be normal and are not checked. Zeros and Pseudo Zeros The value zero in the real and decimal integer formats may be signed either positive or negative, although the sign of a binary integer zero is always positive. For computational purposes, the value of zero always behaves identically, regardless of sign, and typically the fact that a zero may be signed is transparent to the programmer. If necessary, the FXAM instruction may be used to determine a zero's sign. The zeros discussed above are called true zeros; if one of them is loaded or generated in a register, the register is tagged zero. Table 1-10 lists the results of instructions executed with zero operands and also shows how a true zero may be created from nonzero operands. Only the temporary real format may contain a special class of values called pseudo zeros. A pseudo zero is an unnormal whose significand is all zeros, but whose (biased) exponent is nonzero (true zeros have a zero exponent). Neither is a pseudo zero's exponent all ones, since this encoding is reserved for infinities and NANs. A pseudo zero result will be produced if two unnormals, containing a total of more than 64 leading zero bits in their significands, are multiplied together. This is a remote possibility in most applications, but it can happen. Pseudo zero operands behave like unnormals, except in the following cases where they produce the same results as true zeros: ~ Compare and test instructions ~ FRNDINT (round to integer) ~ Division, where the dividend is either a true zero or a pseudo zero (the divisor is a pseudo zero) In addition and subtraction of a pseudo zero and a true zero or another pseudo zero, the pseudo zero(s) behaves like unnormals, except for the determination of the result's sign. The sign is determined as shown in table 1-10 for two true zero operands. Infinity The real formats support signed representations of infinities. These values are encoded with a biased exponent of all ones and a significand of 1{}00...00; if the infinity is in a register, it is tagged special. The significand distinguishes infinities from NANs, including real indefinite. A programmer may code an infinity, or it may be created by the NPX as its masked response to an overflow or a zero divide exception. Note that when rounding is up or down, the masked response may create the largest valid value representable in the destination rather than infinity. See table 1-11 for details. As operands, infinities behave somewhat differently depending on how the infinity control field in the control word is set (see table 1-12). When the projective model of infinity is selected, the infinities behave as a single unsigned representation; because of this, infinity cannot be compared with any value except infinity. In affine mode, the signs of the infinities are observed, and comparisons are possible. Table 1-10. Zero Operands and Results Operation/Operands Result Operation/Operands Result FLD, FBLD Arithmetic and compare operations with binary integers interpret the integer sign in the same manner. Division +0 +0 q0 v q0 Invalid operation -0 -0 qX v q0 Zerodivide FILD Arithmetic and compare operations with binary integers interpret the integer sign in the same manner. +0 v +X, -0 v -X +0 +0 +0 +0 v -X, -0 v +X -0 FST, FSTP -X v -Y, +X v +Y +0, underflow Very small X and very large Y may yield zero, after rounding of true result. NPX signals underflow to warn that zero has been yielded from nonzero operands. +0 +0 -X v +Y, +X v -Y -0, underflow Very small X and very large Y may yield zero, after rounding of true result. NPX signals underflow to warn that zero has been yielded from nonzero operands. -0 -0 +X Severe underflows in storing to short or long real may generate zeros +0 FPREM -X Severe underflows in storing to short or long real may generate zeros -0 q0 rem q0 Invalid operation FBSTP qX rem q0 Invalid operation +0 +0 +0 rem +X, +0 rem -X +0 -0 -0 -0 rem +X, -0 rem -X -0 FIST, FISTP +X rem +Y, +X rem -Y +0 When Y divides into X exactly +0 +0 -X rem -Y, -X rem +Y -0 When Y divides into X exactly -0 +0 +X Small values (3X3 < 1) stored into integers may round to zero +0 FSQRT -X Small values (3X3 < 1) stored into integers may round to zero +0 -0 -0 +0 +0 Addition +0 plus +0 +0 Compare -0 plus -0 -0 q0: +X A < B +0 plus -0, -0 plus +0 *0 Sign is determined by round mode: * = + for nearest, up, or chop * = - for down q0: q0 A = B -X plus +X, +X plus -X *0 Sign is determined by round mode: * = + for nearest, up, or chop * = - for down q0: -X A > B q0 plus qX, qX plus q0 EX E = sign of X FTST Subtraction q0 Zero +0 minus -0 +0 FCHS -0 minus +0 -0 +0 -0 +0 minus +0, -0 minus -0 *0 Sign is determined by round mode: * = + for nearest, up, or chop * = - for down -0 +0 +X minus +X, -X minus -X *0 Sign is determined by round mode: * = + for nearest, up, or chop * = - for down FABS q0 minus qX, qX minus q0 EX E = sign of X q0 +0 F2XM1 Multiplication +0 +0 +0 * +0, -0 * -0 +0 -0 -0 +0 * -0, -0 * +0 -0 FRNDINT +0 * +X, +X * +0 +0 +0 +0 +0 * -X, -X * +0 -0 -0 -0 -0 * +X, +X * -0 -0 FXTRACT -0 * -X, -X * -0 +0 +0 Both +0 +X * +Y, -X * -Y +0, underflow Very small values of X and Y may yield zeros, after rounding of true result. NPX signals underflow to warn that zero has been yielded by nonzero operands. -0 Both -0 +X * -Y, -X * +Y -0, underflow Very small values of X and Y may yield zeros, after rounding of true result. NPX signals underflow to warn that zero has been yielded by nonzero operands. NaN (Not a Number) A NaN (Not a Number) is a member of a class of special values that exist in the real formats only. A NaN has an exponent of 11..11B, may have either sign, and may have any significand except 1{}00..00B, which is assigned to the infinities. A NaN in a register is tagged special. The 80287 will generate the special NaN, real indefinite, as its masked response to an invalid operation exception. This NaN is signed negative; its significand is encoded 1{}100..00. All other NaNs represent programmer-created values. Whenever the NPX uses an operand that is a NaN, it signals an invalid operation exception in its status word. If this exception is masked in the 80287 control word, the 80287's masked exception response is to return the NaN as the operation result. If both operands of an instruction are NaNs, the result is the NaN with the larger absolute value. In this way, a NaN that enters a computation propagates through the computation and will eventually be delivered as the final result. Note, however, that the transcendental instructions do not check their operands, and a NaN will produce an undefined result. By unmasking the invalid operation exception, the programmer can use NaNs to trap to the exception handler. The generality of this approach and the large number of NaN values that are available provide the sophisticated programmer with a tool that can be applied to a variety of special situations. For example, a compiler could use NaNs as references to uninitialized (real) array elements. The compiler could preinitialize each array element with a NaN whose significand contained the index (relative position) of the element. If an application program attempted to access an element that it had not initialized, it would use the NaN placed there by the compiler. If the invalid operation exception were unmasked, an interrupt would occur, and the exception handler would be invoked. The exception handler could determine which element had been accessed, since the operand address field of the exception pointers would point to the NaN, and the NaN would contain the index number of the array element. NaNs could also be used to speed up debugging. In its early testing phase, a program often contains multiple errors. An exception handler could be written to save diagnostic information in memory whenever it was invoked. After storing the diagnostic data, it could supply a NaN as the result of the erroneous instruction, and that NaN could point to its associated diagnostic area in memory. The program would then continue, creating a different NaN for each error. When the program ended, the NaN results could be used to access the diagnostic data saved at the time the errors occurred. Many errors could thus be diagnosed and corrected in one test run. Table 1-11. Masked Overflow Response with Directed Rounding ZDDDDDDDDDDDDDDDDDDDBDDDDDDDDDDBDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD? 3 True Result 3 3 3 CDDDDDDDDDDDDDDBDDDD4 Rounding 3 Result Delivered 3 3Normalization 3Sign3 Mode 3 3 CDDDDDDDDDDDDDDEDDDDEDDDDDDDDDDEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD4 3Normal 3 + 3 Up 3 +l 3 3Normal 3 + 3 Down 3 Largest finite positive number The largest valid representable reals are encoded: exponent: 11...10B significand: (1){}11...10B 3 3Normal 3 - 3 Up 3 Largest finite negative number The largest valid representable reals are encoded: exponent: 11...10B significand: (1){}11...10B 3 3Normal 3 - 3 Down 3 -l 3 3Unnormal 3 + 3 Up 3 +l 3 3Unnormal 3 - 3 Down 3 Largest exponent, result's significand The significand retains its identity as an unnormal; the true result is rounded as usual (effectively chopped toward 0 in this case). The exponent is encoded 11...10B. 3 3Unnormal 3 + 3 Up 3 Largest exponent, result's significand The significand retains its identity as an unnormal; the true result is rounded as usual (effectively chopped toward 0 in this case). The exponent is encoded 11...10B. 3 3Unnormal 3 - 3 Down 3 -l 3 @DDDDDDDDDDDDDDADDDDADDDDDDDDDDADDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDY Table 1-12. Infinity Operands and Results Key to symbols used in this table X = zero or nonzero operand Y = nonzero operand * = sign of original operand E = sign is complement of original operand's sign h = sign is "exclusive or" original operand signs (+ if operands had same sign, - if operands had different signs) Operation Projective Result Affine Result Addition +l plus +l Invalid operation +l -l plus -l Invalid operation -l +l plus -l Invalid operation Invalid operation -l plus +l Invalid operation Invalid operation ql plus qX *l *l qX plus ql *l *l Subtraction +l minus -l Invalid operation +l -l minus +l Invalid operation -l +l minus +l Invalid operation Invalid operation -l minus -l Invalid operation Invalid operation ql minus qX *l *l qX minus ql El El Multiplication ql * ql h h ql * qY h h q0 * ql, ql * q0 Invalid operation Invalid operation Division ql v ql Invalid operation Invalid operation ql v qX h h qX v ql h h FSQRT -l Invalid operation Invalid operation +l Invalid operation +l FPREM ql rem ql Invalid operation Invalid operation ql rem qX Invalid operation Invalid operation qY rem ql *Y *Y q0 rem ql *0 *0 FRNDINT ql *l *l FSCALE ql scaled by ql Invalid operation Invalid operation ql scaled by qX *l *l q0 scaled by ql *0 *0 qY scaled by q Invalid operation Invalid operation FXTRACT ql Invalid operation Invalid operation Compare ql: ql A = B -l < +l ql: qY A ? B (and) invalid operation -l < Y < +l ql: q0 A ? B (and) invalid operation -l < 0 < +l FTST ql A ? B (and) invalid operation *l Indefinite For every 80287 numeric data type, one unique encoding is reserved for representing the special value indefinite. The 80287 produces this encoding as its response to a masked invalid-operation exception. In the case of reals, the indefinite value can be stored and loaded like any NaN, and it always retains its special identity; programmers are advised not to use this encoding for any other purpose. Packed decimal indefinite may be stored by the NPX in a FBSTP instruction; attempting to use this encoding in a FBLD instruction, however, will have an undefined result. In the binary integers, the same encoding may represent either indefinite or the largest negative number supported by the format (-2^(15), -2^(31), or -2^(63)). The 80287 will store this encoding as its masked response to an invalid operation, or when the value in a source register represents or rounds to the largest negative integer representable by the destination. In situations where its origin may be ambiguous, the invalid operation exception flag can be examined to see if the value was produced by an exception response. When this encoding is loaded, or used by an integer arithmetic or compare operation, it is always interpreted as a negative number; thus indefinite cannot be loaded from a packed decimal or binary integer. Encoding of Data Types Tables 1-13 through 1-16 show how each of the special values just described is encoded for each of the numeric data types. In these tables, the least-significant bits are shown to the right and are stored in the lowest memory addresses. The sign bit is always the left-most bit of the highest-addressed byte. Table 1-13. Binary Integer Encodings Class Sign Magnitude ZDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 (Largest) 0 11...11 3 y y Positives y y 3 y y 3 (Smallest) 0 00...01 @DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD Zero 0 00...00 ZDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 (Smallest) 1 11...11 3 y y Negatives y y 3 y y 3 (Largest/Indefinite If this encoding is used as a source operand (as in an integer load or integer arithmetic instruction), the 80287 interprets it as the largest negative number representable in the format: -2^(15), -2^(31), or -2^(63). The 80287 will deliver this encoding to an integer destination in two cases: 1. If the result is the largest negative number 2. As the response to a masked invalid operation exception, in which case it represents the special value integer indefinite.) 1 00...00 @DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD Word: DDD15 bitsDDD Short: DDD31 bitsDDD Long: DDD63 bitsDDD Table 1-14. Packed Decimal Encodings ZDDDDDDDDDDDDDDDDDDD Magnitude DDDDDDDDDDDDDDDDDDDDDDDD? Class Sign digit digit digit digit . . . digit ZDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 (Largest) 0 0000000 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 . . . 1 0 0 1 3 y y y 3 y y y Positives y y y 3 (Smallest) 0 0000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . 0 0 0 1 3 3 Zero 0 0000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . 0 0 0 0 @DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD ZDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 Zero 1 0000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . 0 0 0 0 3 3 (Smallest) 1 0000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . 0 0 0 1 Negatives y y y 3 y y y 3 y y y 3 (Largest) 1 0000000 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 . . . 1 0 0 1 @DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD Indefinite The packed decimal indefinite encoding is stored by FBSTP in response to a masked invalid operation exception. Attempting to load this value via FBLD produces an undefined result. 1 1111111 1 1 1 1 1 1 1 1 U U U U UUUU means bit values are undefined and may contain any value U U U U . . . U U U U DDDD 1 byte DDD DDDDDDDDDDDDDDDDDDDDDDDD 9 bytes DDDDDDDDDDDDDDDDDDDDDD Table 1-15. Real and Long Real Encodings Biased Significand Integer bit is implied and not stored Class Sign Exponent {}ff...ff ZDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 NaNs 0 11...11 11...11 3 y y y 3 y y y 3 y y y 3 0 11...11 00...01 3 DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 l 0 11...11 00...00 3 ZDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 3 Normals 0 11...10 11...11 3 3 y y y Positives 3 y y y 3 3 y y y 3 3 0 00...01 00...00 3 3 DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 Reals Denormals 0 00...00 11...11 3 3 y y y 3 3 y y y 3 3 y y y 3 3 0 00...00 00...01 3 3 DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 3 Zero 0 00...00 00...00 @DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD ZDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 3 Zero 1 00...00 00...00 3 3 DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 3 Denormals 1 00...00 00...01 3 3 y y y 3 3 y y y 3 Reals y y y 3 3 1 00...00 11...11 3 3 DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 3 Normals 1 00...01 00...00 3 3 y y y 3 3 y y y 3 3 y y y 3 3 1 11...10 11...11 Negatives @DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 l 1 11...11 00...00 3 ZDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 3 1 11...11 00...01 3 3 y y y 3 NaNs y y y 3 3 y y y 3 3 DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 3 Indefinite 1 11...11 10...00 3 @DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 y y y 3 y y y 3 y y y 3 1 11...11 11...11 @DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD Short: 3 DDD8 bitsDD 3 DD23 bitsDD 3 Long: 3 DD11 bitsDD 3 DD52 bitsDD 3 Table 1-16. Temporary Real Encodings Biased Significand Integer bit is implied and not stored Class Sign Exponent 1{}ff...ff ZDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 NaNs 0 11...11 111...11 3 y y y 3 y y y 3 y y y 3 0 11...11 100...01 3 DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 l 0 11...11 100...00 3 ZDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 3 0 11...10 Normals 3 3 y y 111...11 3 3 y y y 3 3 y y y 3 3 y y y 3 3 y y y 3 3 y y 100...00 3 3 y y DDDDDDDDDDDDDD Positives 3 y y Unnormals 3 3 y y 011...11 3 Reals y y y 3 3 y y y 3 3 y y y 3 3 0 00...01 000...00 3 3 DDDDDDDDDDDDDD 3 3 Denormals 3 3 0 00...00 011...11 3 3 y y y 3 3 y y y 3 3 y y y 3 3 0 00...00 000...01 3 CDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 3 Zero 0 00...00 000...00 @DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD ZDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 3 Zero 1 00...00 000...00 3 CDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 3 Denormals 3 3 1 00...00 000...01 3 3 y y y 3 3 y y y 3 3 y y y 3 3 1 00...00 011...11 3 3 DDDDDDDDDDDDDD 3 3 1 00...01 Unnormals 3 3 y y 000...00 3 3 y y y 3 Reals y y y 3 3 y y y 3 3 y y 011...11 3 3 y y 3 3 DDDDDDDDDDDDDD Negatives 3 y y Normals 3 3 y y 100...00 3 3 y y y 3 3 y y y 3 3 y y y 3 3 1 11...10 11111...11 3 @DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 l 1 11...11 100...00 3 ZDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 3 1 11...11 100...00 3 3 y y y 3 3 y y y 3 3 y y y 3 3 DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 NaNs Indefinite 1 11...11 110...00 3 3 DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3 3 y y y 3 3 y y y 3 3 y y y 3 3 1 11...11 111...11 @DDDDDDADDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 3DD15 bitsDD3DD64 bitsDD3 Numeric Exceptions Whenever the 80287 NPX attempts a numeric operation with invalid operands or produces a result that cannot be represented, the 80287 recognizes a numeric exception condition. Altogether, the 80287 checks for the following six classes of exceptions while executing numeric instructions: 1. Invalid operation 2. Divide-by-zero 3. Denormalized operand 4. Numeric overflow 5. Numeric underflow 6. Inexact result (precision) Invalid Operation The 80287 reports an invalid operation if any of the following occurs: ~ An attempt to load a register that is not empty (stack overflow). ~ An attempt to pop an operand from an empty register (stack underflow). ~ An operand is a NaN. ~ The operands cause the operation to be indeterminate (square root of a negative number, 0/0). An invalid operation generally indicates a program error. Zero Divisor If an instruction attempts to divide a finite nonzero operand by zero, the 80287 will report a zero divide exception. Denormalized Operand If an instruction attempts to operate on a denormal, the NPX reports the denormalized operand exception. This exception allows users to implement in software an option of the proposed IEEE standard specifying that operands must be prenormalized before they are used. Numeric Overflow and Underflow If the exponent of a numeric result is too large for the destination real format, the 80287 signals a numeric overflow. Conversely, if the exponent of a result is too small to be represented in the destination format, a numeric underflow is signaled. If either of these exceptions occur, the result of the operation is outside the range of the destination real format. Typical algorithms are most likely to produce extremely large and small numbers in the calculation of intermediate, rather than final, results. Because of the great range of the temporary real format (recommended as the destination format for intermediates), overflow and underflow are relatively rare events in most 80287 applications. Inexact Result If the result of an operation is not exactly representable in the destination format, the 80287 rounds the number and reports the precision exception. For example, the fraction 1/3 cannot be precisely represented in binary form. This exception occurs frequently and indicates that some (generally acceptable) accuracy has been lost; it is provided for applications that need to perform exact arithmetic only. Handling Numeric Errors When numeric errors occur, the NPX takes one of two possible courses of action: ~ The NPX can itself handle the error, producing the most reasonable result and allowing numeric program execution to continue undisturbed. ~ A software exception handler can be invoked by the CPU to handle the error. Each of the six exception conditions described above has a corresponding flag bit in the 80287 status word and a mask bit in the 80287 control word. If an exception is masked (the corresponding mask bit in the control word = 1), the 80287 takes an appropriate default action and continues with the computation. If the exception is unmasked (mask = 0), the 80287 asserts the ERROR output to the 80286 to signal the exception and invoke a software exception handler. The NPX reports an exception by setting the corresponding flag in the NPX status word to 1. The NPX then checks the corresponding exception mask in the control word to determine if it should "field" the exception (mask = 1), or if it should signal the exception to the CPU to invoke a software exception handler (mask = 0). If the mask is set, the exception is said to be masked (from user software), and the NPX executes its on-chip masked response for that exception. If the mask is not set (mask = 0), the exception is unmasked, and the NPX performs its unmasked response. The masked response always produces a standard result, then proceeds with the instruction. The unmasked response always traps to a software exception handler, allowing the CPU to recognize and take action on the exception. Table 1-17 gives a complete description of all exception conditions and the NPX's masked response. Note that when exceptions are masked, the NPX may detect multiple exceptions in a single instruction, because it continues executing the instruction after performing its masked response. For example, the 80287 could detect a denormalized operand, perform its masked response to this exception, and then detect an underflow. Table 1-17. Exception Conditions and Masked Responses DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD Condition Masked Response DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD Invalid Operation DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD Source register is tagged empty Return real indefinite. (usually due to stack underflow). Destination register is not tagged Return real indefinite empty (usually due to stack (overwrite destination value). overflow). One or both operands is a NaN. Return NaN with larger absolute value (ignore signs). (Compare and test operations only): Set condition codes "not one or both operands is a NaN. comparable." (Addition operations only): closure Return real indefinite. is affine and operands are opposite-signed infinities; or closure is projective and both operands are l (signs immaterial). (Subtraction operations only): Return real indefinite. closure is affine and operands are like-signed infinities; or closure is projective and both operands are l (signs immaterial). (Multiplication operations only): Return real indefinite. l * 0; or 0 * l. (Division operations only): Return real indefinite. l v l; or 0 v 0; or 0 v pseudo zero; or divisor is denormal or unormal. (FPREM instruction only): modulus Return real indefinite, set (divisor) is unnormal or denormal; condition code = "complete or dividend is l. remainder." (FSQRT instruction only): operand Return real indefinite. is nonzero and negative; or operand is denormal or unnormal; or closure is affine and operand is -l; or closure is projective and operand is l. (Compare operations only): closure Set condition code = "not is projective and l is being comparable." compared with 0, a normal or l. (FTST instruction only): closure is Set condition code = "not projective and operand is l. comparable." (FIST, FISTP instructions only): Store integer indefinite. source register is empty, a NaN, denormal, unnormal, l, or exceeds representable range of destination. (FBSTP instruction only): source Stored packed decimal register is empty, a NaN, denormal, indefinite. unnormal, l, or exceeds 18 decimal digits. (FST, FSTP instructions only): Store real indefinite. destination is short or long real and source register is an unnormal with exponent in range. (FXCH instruction only): one or Change empty register(s) to both registers is tagged empty. real indefinite and then perform exchange. DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD Condition Masked Response DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD Denormalized Operand DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD (FLD instruction only): source No special action; load as usual. operand is denormal. (Arithmetic operations only): one Convert (in a work area) the or both operands is denormal. operand to the equivalent unnormal and proceed. (Compare and test operations only): Convert (in a work area) any one or both operands is denormal denormal to the equivalent or unnormal other than pseudo unnormal; normalize as much as zero). possible, and proceed with operation. DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD Zero Divide DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD (Division operations only): Return l signed with "exclusive or" divisor = 0. of operand signs. DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD Overflow DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD (Arithmetic operations only): Return properly signed l and signal rounding is nearest or chop, and precision exception. exponent of true result > 16,383. (FST, FSTP instructions only): Return properly signed l and signal rounding is nearest or chop, and precision exception. exponent of true result > +127 (short real destination) or > +1023 (long real destination). DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD Underflow DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD (Arithmetic operations only): Denormalize until exponent rises to exponent of true result < -16,382 -16,382 (true), round significand (true). to 64 bits. If denormalized rounded significand = 0, then return true 0; else, return denormal (tag = special, biased exponent = 0). (FST, FSTP instructions only): Denormalize until exponent rises to destination is short real and -126 (true), round significand to exponent of true result < -126 24 bits, store true 0 if (true). denormalized rounded significand = 0; else, store denormal (biased exponent = 0). (FST, FSTP instructions only): Denormalize until exponent rises to destination is lo